Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-32
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1.10 ARM1176JZF-S instruction set summary
This section provides:
•an Extended ARM instruction set summary on page 1-33
•a Thumb instruction set summary on page 1-44.
Table 1-6 lists a key to the ARM and Thumb instruction set tables.
The ARM1176JZF-S processor implements the ARM architecture v6 with ARM Jazelle
technology. For a description of the ARM and Thumb instruction sets, see the ARM Architecture
Reference Manual. Contact ARM Limited for complete descriptions of all instruction sets.
Table 1-6 Key to instruction set tables
Symbol Description
{!}
Update base register after operation if ! present.
{^}
For all STMs and LDMs that do not load the PC, stores or restores the User mode banked registers
instead of the current mode registers if ^ present, and sets the S bit. For LDMs that load the PC,
indicates that the CPSR is loaded from the SPSR.
B
Byte operation.
H
Halfword operation.
T
Forces execution to be handled as having User mode privilege. Cannot be used with pre-indexed
addresses.
x Selects HIGH or LOW 16 bits of register Rm. T selects the HIGH 16 bits,
T = top, and B selects the LOW 16 bits, B = bottom.
y Selects HIGH or LOW 16 bits of register Rs. T selects the HIGH 16 bits,
T = top, and B selects the LOW 16 bits, B = bottom.
{cond}
Updates condition flags if cond present. See Table 1-15 on page 1-43.
{field}
See Table 1-14 on page 1-43.
{S}
Sets condition codes, optional.
<a_mode2>
See Table 1-8 on page 1-40.
<a_mode2P>
See Table 1-9 on page 1-41.
<a_mode3>
See Table 1-10 on page 1-42.
<a_mode4>
See Table 1-11 on page 1-42.
<a_mode5>
See Table 1-12 on page 1-42.
<cp_num>
One of the coprocessors p0 to p15.
<effect>
Specifies the effect required on the interrupt disable bits, A, I, and F in the CPSR:
IE = Interrupt enable
ID = Interrupt disable.
<
iflags
> specifies the bits affected if
<effect>
is specified.
<endian_specifier>
BE = Set E bit in instruction, set CPSR E bit.
LE = Reset E bit in instruction, clear CPSR E bit.
<HighReg>
Specifies a register in the range R8 to R15.
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