ARM ARM1176JZF-S - Table 8-28 Noncacheable LDM6, Noncacheable Memory or Cache Disabled; Noncacheable LDM6 from Word 3, 4, 5, 6, or 7; Table 8-30 Noncacheable LDM7, Strongly Ordered or Device Memory; Table 8-31 Noncacheable LDM7, Noncacheable Memory or Cache Disabled

Level Two Interface
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8.5.10 Noncacheable LDM7
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM7s addressing word 0 or 1 are shown in:
• Table 8-30 for a load from Strongly Ordered or Device memory
• Table 8-31 for a load from Noncacheable memory or when the cache is disabled.
A Noncacheable LDM7 addressing words 2 to 7 is split into two operations as shown in
Table 8-32.
Table 8-28 Noncacheable LDM6, Noncacheable memory or cache disabled
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 3 data transfers
0x04 , word 1 0x04 Incr 64-bit 4 data transfers
0x08 , word 2 0x08 Incr 64-bit 3 data transfers
Table 8-29 Noncacheable LDM6 from word 3, 4, 5, 6, or 7
Address[4:0] Operations
0x0C , word 3 LDM5 from 0x0C + LDR from 0x00
0x10
, word 4 LDM4 from 0x10 + LDM2 from 0x00
0x14
, word 5 LDM3 from 0x14 + LDM3 from 0x00
0x18
, word 6 LDM2 from 0x18 + LDM4 from 0x00
0x1C
, word 7 LDR from 0x1C + LDM5 from 0x00
Table 8-30 Noncacheable LDM7, Strongly Ordered or Device memory
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 32-bit 7 data transfers
0x04 , word 1 0x04 Incr 32-bit 7 data transfers
Table 8-31 Noncacheable LDM7, Noncacheable memory or cache disabled
Address[4:0] ARADDRRW ARBURSTRW ARSIZERW ARLENRW
0x00 , word 0 0x00 Incr 64-bit 4 data transfers
0x04 , word 1 0x04 Incr 64-bit 4 data transfers
Table 8-32 Noncacheable LDM7 from word 2, 3, 4, 5, 6, or 7
Address[4:0] Operations
0x08 , word 2 LDM6 from 0x08 + LDR from 0x00
0x0C
, word 3 LDM5 from 0x0C + LDM2 from 0x00
0x10
, word 4 LDM4 from 0x10 + LDM3 from 0x00