Level One Memory System
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-4
ID012310 Non-Confidential, Unrestricted Access
Figure 7-1 Level one cache block diagram
7.2.1 Features of the cache system
The level one cache system has the following features:
• The cache is a Harvard implementation.
• The caches are lockable at a granularity of a cache way, using Format C lockdown. See
Cache control and configuration on page 3-7.
• Cache replacement policies are Pseudo-Random or Round-Robin, as controlled by the RR
bit in CP15 register c1. Round-Robin uses a single counter for all sets, that selects the way
used for replacement.
• Cache line allocation uses the cache replacement algorithm when all cache lines are valid.
If one or more lines is invalid, then the invalid cache line with the lowest way number is
allocated to in preference to replacing a valid cache line. This mechanism does not
allocate to locked cache ways unless all cache ways are locked. See Cache miss handling
when all ways are locked down on page 7-6.
• Cache lines can contain either Secure or Non-secure data and the NS Tag, that the
MicroTLB provides, indicates when the cache line comes from Secure or Non-secure
memory.
• Cache lines can be either Write-Back or Write-Through, determined by the MicroTLB
entry.
• Only read allocation is supported.
DATARAM
TAGRAM
TCM
Comparator
Way
select
Write buffer data (1-2 words)
Write buffer addresses
Micro
TLB
Cache
hit
Data
out
Micro TLB
miss and
Data Abort
RAMSet base address and size
CP15
interface
Virtual
address
Write
data
To Next Page
Loading...
Need help?
General
