Preface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. xxii
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About this book
This book is for ARM1176JZF-S processor. In this manual the generic term processor means
the ARM1176JZF-S processor.
Product revision status
The rnpn identifier indicates the revision status of the product described in this book, where:
rn Identifies the major revision of the product.
pn Identifies the minor revision or modification status of the product.
Intended audience
This document has been written for hardware and software engineers implementing the
processor system designs. It provides information to enable designers to integrate the processor
into a target system as quickly as possible.
Using this book
This book is organized into the following chapters:
Chapter 1 Introduction
Read this for an introduction to the processor and descriptions of the major
functional blocks.
Chapter 2 Programmer’s Model
Read this for a description of the processor registers and programming details.
Chapter 3 System Control Coprocessor
Read this for a description of the processor’s system control coprocessor CP15
registers and programming details.
Chapter 4 Unaligned and Mixed-endian Data Access Support
Read this for a description of the processor support for unaligned and
mixed-endian data accesses.
Chapter 5 Program Flow Prediction
Read this for a description of the functions of the processor’s Prefetch Unit,
including static and dynamic branch prediction and the return stack.
Chapter 6 Memory Management Unit
Read this for a description of the processor’s Memory Management Unit (MMU)
and the address translation process.
Chapter 7 Level One Memory System
Read this for a description of the processor’s level one memory system, including
caches, TCM, DMA, TLBs, and write buffer.
Chapter 8 Level Two Interface
Read this for a description of the processor’s level two memory interface and the
peripheral port.
Chapter 9 Clocking and Resets
Read this for a description of the processor’s clocking modes and the reset
signals.
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