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Debug

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• Any WRP can be linked with any BRP with context ID comparison capability. Several

BRPs, holding IMVAs, and WRPs can be linked with the same context ID capable BRP.

• If a WRP is linked with a BRP that is not configured for context ID comparison and

linking, it is architecturally Unpredictable if a watchpoint debug event is generated or not.

For ARM1176JZF-S processors the watchpoint debug event is not generated. BCR[22:20]

fields of the BRP must be set to b011.

• If a WRP is linked with a BRP that is not implemented, it is architecturally Unpredictable

if a watchpoint debug event is generated or not. For ARM1176JZF-S processors the

watchpoint debug event is not generated.

• If a WRP is linked with a BRP and they are not both enabled, BCR[0] and WCR[0] set, it

does not generate a watchpoint debug event.

13.3.11 CP14 c10, Debug State Cache Control Register

The Debug State Cache Control Register controls cache behavior in Debug state:

MRC p14, 0, <Rd>, c0, c10, 0

MCR p14, 0, <Rd>, c0, c10, 0

Table 13-17 lists the functional bits in the register.

The effect of these bits only applies in Debug state. The operation under control only occurs if

it is enabled in both this register and by the corresponding bit in the Cache Behavior Override

13.3.12 CP14 c11, Debug State MMU Control Register

The Debug State MMU Control Register controls main and micro TLB behavior in Debug state:

MRC p14, 0, <Rd>, c0, c11, 0

MCR p14, 0, <Rd>, c0, c11, 0

Table 13-18 on page 13-24 lists the functional bits in the register.

Table 13-17 Debug State Cache Control Register bit functions

Bits Reset value Name Description

[31:3] UNP/SBZ - Reserved.

[2] 0 nWT Not Write-Through:

1 = Normal operation of regions marked as Write-Back in Debug state.

0 = force Write-Through behavior for regions marked as Write-Back in Debug state.

[1] 0 nIL No Instruction Cache Line-Fill:

1 = Normal operation of Instruction Cache line fills in Debug state.

0 = Instruction Cache line-fill disabled in Debug state.

[0] 0 nDL No Data/Unified Cache Line-Fill:

1 = Normal operation of Data/Unified Cache line-fills in Debug state.

0 = Data/Unified Cache line-fill disabled in Debug state.

ARM ARM1176JZF-S User Manual

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