VFP Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-5
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• In default NaN mode, NaNs are handled completely within the hardware without support
code assistance. SNaNs in an arithmetic CDP operation set the IOC flag, FPSCR[0]. NaN
handling by data transfer and nonarithmetic CDP instructions is the same as in
full-compliance mode. Arithmetic CDP instructions involving NaN operands return the
default NaN regardless of the fractions of any NaN operands.
Table 20-2 summarizes the effects of NaN operands on instruction execution.
Comparisons
Comparison results modify condition code flags in the FPSCR register. The FMSTAT
instruction transfers the current condition code flags in the FPSCR register to the ARM11 CPSR
register. See the ARM Architecture Reference Manual for mapping of IEEE 754 standard
predicates to ARM conditions. The condition code flags used are chosen so that subsequent
conditional execution of ARM instructions can test the predicates defined in the IEEE 754
standard.
The VFP11 coprocessor handles most comparisons of numeric values in hardware, generating
the appropriate condition code depending on whether the result is less than, equal to, or greater
than. When the VFP11 coprocessor is not in flush-to-zero mode, comparisons involving
subnormal operands bounce to support code.
Table 20-2 QNaN and SNaN handling
Instruction
type
Default
NaN
mode With QNaN operand With SNaN operand
Arithmetic CDP
Off
INV
a
set. Bounce to support code to
process operation.
INV set. Bounce to support code to process
operation.
On No bounce. Default NaN returns.
IOC
b
set. If IOE
c
set, bounce to Invalid
Operation user trap handler. If IOE clear,
default NaN returns.
Nonarithmetic
CDP
Off
NaN passes to destination with sign changed as appropriate.
On
FCMP(Z)
Off INV set. Bounce to support code to process
operation.
INV set. Bounce to support code to process
operation.
On No bounce. Unordered compare. IOC set. If IOE set, bounce to Invalid
Operation user trap handler. If IOE clear,
unordered compare.
FCMPE(Z)
Off INV set. Bounce to support code to process
operation.
INV set. Bounce to support code to process
operation.
On IOC set. If IOE set, bounce to Invalid
Operation user trap handler. If IOE clear,
unordered compare.
IOC set. If IOE set, bounce to Invalid
Operation user trap handler. If IOE clear,
unordered compare.
Load/store
Off
All NaNs transferred. No bounce.
On
a. INV is the Input exception flag, FPEXC[7].
b. IOC is the Invalid Operation cumulative exception flag, FPSCR[0].
c. IOE is the Invalid Operation exception trap enable bit, FPSCR[8].
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