ARM ARM1176JZF-S User Manual

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-133
ID012310 Non-Confidential, Unrestricted Access
Table 3-135 lists the results of attempted access for each mode.
To access the Secure User and Non-secure Access Validation Control Register read or write
CP15 with:
• Opcode_1 set to 0
• CRn set to c15
• CRm set to c9
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c15, c9, 0 ; Read Secure User and Non-secure Access Validation Control Register
MCR p15, 0, <Rd>, c15, c9, 0 ; Write Secure User and Non-secure Access Validation Control Register
3.2.51 c15, Performance Monitor Control Register
The purpose of the Performance Monitor Control Register is to control the operation of:
• the Cycle Counter Register
• the Count Register 0
• the Count Register 1.
Table 3-136 on page 3-134 lists the purpose of the individual bits in the register.
The Performance Monitor Control Register is:
• in CP15 c15
• a 32-bit read/write register common to Secure and Non-secure worlds
• accessible in User and Privileged modes.
Figure 3-73 shows the bit arrangement for the Performance Monitor Control Register.
Figure 3-73 Performance Monitor Control Register format
Table 3-135 Results of access to the Secure User and Non-secure Access
Validation Control Register
Secure Privileged
Non-secure Privileged User
Read Write
Data Data Undefined exception Undefined exception
ESBZ/UNP
31 28 27 20 19 12 11 7 6 4 3 2 1 0
EvtCount0 EvtCount1 X
S
B
Z
C PD
10 8
C
C
R
C
R
1
C
R
0
9
E
C
C
E
C
1
E
C
0
5

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English