Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-33
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8.5.33 Cacheable Write-Through or Noncacheable STM10
An STM10 over the Data Read/Write Interface is split into two or three operations as shown in
Table 8-63.
8.5.34 Cacheable Write-Through or Noncacheable STM11
An STM11 over the Data Read/Write Interface is split into two or three operations as shown in
Table 8-64.
0x0C
, word 3 STM5 to
0x0C
+ STM4 to
0x00
0x10
, word 4 STM4 to
0x10
+ STM5 to
0x00
0x14
, word 5 STM3 to
0x14
+ STM6 to
0x00
0x18
, word 6 STM2 to
0x18
+ STM7 to
0x00
0x1C
, word 7 STR to
0x1C
+ STM8 to
0x00
Table 8-62 Cacheable Write-Through or Noncacheable STM9 (continued)
Address[4:0] Operations
Table 8-63 Cacheable Write-Through or Noncacheable STM10
Address[4:0] Operations
0x00
, word 0 STM8 to
0x00
+ STM2 to
0x00
0x04
, word 1 STM7 to
0x04
+ STM3 to
0x00
0x08
, word 2 STM6 to
0x08
+ STM4 to
0x00
0x0C
, word 3 STM5 to
0x0C
+ STM5 to
0x00
0x10
, word 4 STM4 to
0x10
+ STM6 to
0x00
0x14
, word 5 STM3 to
0x14
+ STM7 to
0x00
0x18
, word 6 STM2 to
0x18
+ STM8 to
0x00
0x1C
, word 7 STR to
0x1C
+ STM8 to
0x00
+ STR to
0x00
Table 8-64 Cacheable Write-Through or Noncacheable STM11
Address[4:0] Operations
0x00
, word 0 STM8 to
0x00
+ STM3 to
0x00
0x04
, word 1 STM7 to
0x04
+ STM4 to
0x00
0x08
, word 2 STM6 to
0x08
+ STM5 to
0x00
0x0C
, word 3 STM5 to
0x0C
+ STM6 to
0x00
0x10
, word 4 STM4 to
0x10
+ STM7 to
0x00
0x14
, word 5 STM3 to
0x14
+ STM8 to
0x00
0x18
, word 6 STM2 to
0x18
+ STM8 to
0x00
+ STR to
0x00
0x1C
, word 7 STR to
0x1C
+ STM8 to
0x00
+ STM2 to
0x00
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