Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-10
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Note
The completion signal occurs once for each burst, not for each individual data transfer within
the burst.
8.3.2 Signal name suffixes
The signal name for each of the interfaces denotes the interface that it applies to. The signals
have one of these suffixes:
I Instruction Fetch Interface.
D DMA Interface.
RW Data Read/Write Interface.
P Peripheral Interface.
The second character in the signal name indicates if the data direction is a read, R, or write, W.
For example, AxSIZE[2:0] is called ARSIZEI[2:0] for reads in the Instruction Fetch Interface.
8.3.3 Address channel signals
The address channel control signals in the processor are:
• AxLEN[3:0]
• AxSIZE[2:0] on page 8-11
• AxBURST[1:0] on page 8-11
• AxLOCK[1:0] on page 8-11
• AxCACHE[3:0] on page 8-12
• AxPROT[2:0] on page 8-12
• AxSIDEBAND[4:0] on page 8-13.
AxLEN[3:0]
The AxLEN[3:0] signal indicates the number of transfers in a burst. Table 8-2 shows the values
of AxLEN that the processor uses.
Table 8-2 AxLEN[3:0] encoding
AxLEN[3:0] Number of data transfers
b0000 1
b0001 2
b0010 3
b0011 4
b0100 5
b0101 6
b0110 7
b0111 8
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