ARM ARM1176JZF-S User Manual

Level Two Interface
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-26
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8.5.20 Half-line Write-Back
Table 8-43 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for half-line Write-Backs over the Data Read/Write Interface.
8.5.21 Full-line Write-Back
Table 8-44 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for full-line Write-Backs, evicted cache line valid and both halves dirty, over the
Data Read/Write Interface.
Table 8-43 Half-line Write-Back
Write address
[4:0]
Description
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW
0x00 - 0x07 Evicted cache line valid
and lower half dirty
0x00 Incr 64-bit 2 data transfers
Evicted cache line valid
and upper half dirty
0x10 Incr 64-bit 2 data transfers
0x08 - 0x0F Evicted cache line valid
and lower half dirty
0x08 Wrap 64-bit 2 data transfers
Evicted cache line valid
and upper half dirty
0x10 Incr 64-bit 2 data transfers
0x10 - 0x17 Evicted cache line valid
and lower half dirty
0x00 Incr 64-bit 2 data transfers
Evicted cache line valid
and upper half dirty
0x10 Incr 64-bit 2 data transfers
0x18 - 0x1F Evicted cache line valid
and lower half dirty
0x00 Incr 64-bit 2 data transfers
Evicted cache line valid
and upper half dirty
0x18 Wrap 64-bit 2 data transfers
Table 8-44 Full-line Write-Back
Write address [4:0]
AWADDRR
W
AWBURSTR
W
AWSIZERW AWLENRW
0x00 - 0x07 0x00 Incr 64-bit 4 data transfers
0x08 - 0x0F 0x08 Wrap 64-bit 4 data transfers
0x10 - 0x17 0x10 Wrap 64-bit 4 data transfers
0x18 - 0x1F 0x18 Wrap 64-bit 4 data transfers

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English