Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-20
ID012310 Non-Confidential, Unrestricted Access
The VFP supports a wide range of single and double precision operations, including ABS, NEG,
COPY, MUL, MAC, DIV, and SQRT. The VFP effectively executes most of these in a single
cycle. Table 1-2 lists the exceptions. These issue latencies also apply to individual elements in
a vector operation.
Compliance with the IEEE 754 standard
The VFP supports all five floating point exceptions defined by the IEEE 754 standard:
• invalid operation
• divide by zero
•overflow
• underflow
• inexact.
You can individually enable or disable these exception traps. If disabled, the default results
defined by IEEE 754 are returned. All rounding modes are supported, and basic single and basic
double formats are used.
For full compliance, the VFP requires support code to handle arithmetic where operands or
results are de-norms. This support code is normally installed on the Undefined instruction
exception handler.
Flush-to-zero mode
A flush-to-zero mode is provided where a default treatment of de-norms is applied. Table 1-3
lists the default behavior in flush-to-zero mode.
Operations not supported
The following operations are not directly supported by the VFP:
• remainder
• binary (decimal) conversions
• direct comparisons between single and double-precision values.
These are normally implemented as C library functions.
Table 1-2 Double-precision VFP operations
Instruction types Issue latency
DP MUL and MAC 2 cycle
SP DIV, SQRT 14 cycles
DP DIV, SQRT 28 cycles
All other instructions 1 cycle
Table 1-3 Flush-to-zero mode
Operation Flush-to-zero
De-norm operand(s) Treated as 0+. Inexact flag set.
De-norm result Returned as 0+. Inexact Flag set.
To Next Page
Loading...
Need help?
General
