System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-108
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Figure 3-60 DMA User Accessibility Register format
Table 3-107 lists how the bit values correspond with the DMA User Accessibility Register.
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. The processor can only access this register in Privileged modes.
Table 3-108 lists the results of attempted access for each mode.
To access the DMA User Accessibility Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c11
• CRm set to c1
• Opcode_2 set to0.
For example:
MRC p15, 0, <Rd>, c11, c1, 0 ; Read DMA User Accessibility Register
MCR p15, 0, <Rd>, c11, c1, 0 ; Write DMA User Accessibility Register
The registers that you can access in User mode when the U bit = 1 for the current channel are:
• c11, DMA enable registers on page 3-110
• c11, DMA Control Register on page 3-112
• c11, DMA Internal Start Address Register on page 3-114
• c11, DMA External Start Address Register on page 3-115
• c11, DMA Internal End Address Register on page 3-116
• c11, DMA Channel Status Register on page 3-117.
U
0
SBZ/UNP
31 210
U
1
Table 3-107 DMA User Accessibility Register bit functions
Bits Field name Function
[31:2] - UNP/SBZ.
[1] U1 Indicates if a User mode process can access the registers for channel 1:
0 = User mode cannot access channel 1. User mode accesses cause an Undefined exception.
This is the reset value.
1 = User mode can access channel 1.
[0] U0 Indicates if a User mode process can access the registers for channel 0:
0 = User mode cannot access channel 0. User mode accesses cause an Undefined exception.
This is the reset value.
1 = User mode can access channel 0.
Table 3-108 Results of access to the DMA User Accessibility Register
DMA bit
Secure Privileged Non-secure Privileged
User
Read Write Read Write
0 Data Data Undefined exception Undefined exception Undefined exception
1 Data Data Data Data Undefined exception