ARM ARM1176JZF-S - Table 3-146 System Validation Cache Size Mask Register Bit Functions; Figure 3-75 System Validation Cache Size Mask Register Format

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System Control Coprocessor

ID012310 Non-Confidential, Unrestricted Access

3.2.57 c15, System Validation Cache Size Mask Register

The purpose of the System Validation Cache Size Mask Register is to change the apparent size

of the caches and TCMs as they appear to the processor, for validation by simulation. It does not

change the physical size of the caches and TCMs in a manufactured device.

The System Validation Cache Size Mask Register is:

• in CP15 c15

• a 32 bit read/write register common to the Secure and Non-secure worlds

• accessible in User and Privileged modes.

Figure 3-75 shows the arrangement of bits for the System Validation Cache Size Mask Register.

Figure 3-75 System Validation Cache Size Mask Register format

Table 3-146 lists how the bit values correspond with the System Validation Cache Size Mask

SBZ

31 15 14 12 11 10 8 7 6 4 3 2 0

DTCM

ITCM

DCache

ICache

Write enable

Table 3-146 System Validation Cache Size Mask Register bit functions

Bits Field name Function

[31] Write enable Enables the update of the Cache and TCM sizes:

0 = The Cache and TCM sizes are not changed, reset value.

1 = The Cache and TCM sizes take the new values that the DTCM, ITCM, DCache and ICache

fields of this register specify.

Note

This is bit is write access only and Read As Zero.

[30:15] SBZ UNP/SBZ.

[14:12] DTCM Specifies apparent size of Data TCM and apparent number of Data TCM banks, as it appears

to the processor. All other values are reserved:

b000 = Not present

b011 = 1 bank, 4KB

b100 = 2 banks, 4KB each

b101 = 2 banks, 8KB each

b110 = 2 banks, 16KB each

b111 = 2 banks, 32KB each.

[11] SBZ UNP/SBZ.

[10:8] ITCM Specifies apparent size of Instruction TCM and apparent number of Instruction TCM banks, as

it appears to the processor. All other values are reserved: