Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-19
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16.11 Load and Store Double instructions
This section describes the cycle timing behavior for the LDRD and STRD instructions
The LDRD and STRD instructions:
• Are two-cycle issue if either a negative register offset or a shift other than LSL #2 is used.
Only the offset register is an Early Reg.
• Are single-cycle issue if either a constant offset is used or if a register offset with no shift,
or shift by 2 is used. Both the base and any offset register are Early Regs.
• Take only one memory cycle if the address is doubleword aligned.
• Take two memory cycles if the address is not doubleword aligned.
The updated base register has a result latency of one. For back-to-back load/store instructions
with base write back, the updated base is available to the following load/store instruction with a
result latency of 0.
To prevent instructions after a STRD from writing to a register before it has stored that register,
the STRD registers have a lock latency that determines how many cycles it is before a
subsequent instruction that writes to that register can start.
Table 16-16 lists the cycle timing behavior for LDRD and STRD instructions.
Table 16-17 lists the explanation of
<addr_md_1cycle>
and
<addr_md_2cycle>
that Table 16-16
uses.
Table 16-16 Load and Store Double instructions cycle timing behavior
Example instruction
Cycle
s
Memory cycles
Result latency
(LDRD)
Register lock latency
(STRD)
Address is double-word aligned
LDRD R1, <addr_md_1cycle>
a
11 3/3 1,2
LDRD R1, <addr_md_2cycle>
a
22 4/4 2,3
Address not double-word aligned
LDRD R1, <addr_md_1cycle>
a
12 3/4 1,2
LDRD R1, <addr_md_2cycle>
a
23 4/5 2,3
a. Table 16-17 for an explanation of
<addr_md_1cycle>
and
<addr_md_2cycle>
.
T
able
16-17 <addr_md
_1cycle> and <addr_md_2cycle> L
DRD
example instruction explanation
Example instruction Early Reg Comment
<addr_md_1cycle>
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