Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-18
ID012310 Non-Confidential, Unrestricted Access
16.10.1 Base register update
The base register update for load or store instructions occurs in the ALU pipeline. To prevent an
interlock for back-to-back load or store instructions reusing the same base register, there is a
local forwarding path to recycle the updated base register around the ADD stage.
For example, the following instruction sequence take three cycles to execute:
LDR R5, [R2, #4]!
LDR R6, [R2, #0x10]!
LDR R7, [R2, #0x20]!
LDR <Rd>, [<Rn>, -<Rm>] (!) <Rm>
If negative register offset, or shift other than LSL #2 then
two-issue cycles.
LDR <Rd>, [Rm, -<Rm> <shf> <cns>] (!) <Rm>
LDR <Rd>, [<Rn>], -<Rm> <Rm>
LDR <Rd>, [<Rn>], -<Rm> <shf> <cns> <Rm>
T
able
16-15 <addr_md_1cy
cle> and <addr_md
_2cycle>
LDR example instruction explanation (continued)Example instruction Early Reg Comment
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