ARM ARM1176JZF-S - Figure 4-7 Load Signed Halfword, Big-Endian; Figure 4-8 Store Halfword, Little-Endian

Unaligned and Mixed-endian Data Access Support
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Figure 4-7 Load signed halfword, big-endian
In Figure 4-7, SE0 means bit 15, B0 bit [7], sign extended.
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.8 Store halfword, little-endian
The low 16 bits of the general-purpose register are stored into the memory with bits [7:0] written
to the addressed byte in memory, bits [15:8] to the incremental byte address in memory, as
Figure 4-8 shows.
Figure 4-8 Store halfword, little-endian
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
4.3.9 Store halfword, big-endian
The low 16 bits of the general-purpose register are stored into the memory with bits [15:8]
written to the addressed byte in memory, bits [7:0] to the incremental byte address in memory,
as Figure 4-9 on page 4-10 shows.
B1
B0
Memory Register
31 23 15 7 0
Address
A[31:0]
70
SE0 SE0 B0 B1
+1 lsbyte
msbyte
Register
31 23 15 7 0
x x b1 b0
b1
b0
Memory
Address
A[31:0]
70
+1 msbyte
lsbyte