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Memory Management Unit

ID012310 Non-Confidential, Unrestricted Access

Figure 6-1 shows the memory ordering between two explicit accesses A1 and A2, where A1

occurs before A2 in program order. The symbols used in the figure are as follows:

< Accesses must occur strictly in program order. That is, A1 must occur strictly

before A2. It must be impossible to tell otherwise from observation of the

read/write values and side effects caused by the memory accesses.

? Accesses can occur in any order, provided that the requirements of uniprocessor

semantics are met, for example respecting dependencies between instructions

within a single processor.

Figure 6-1 Memory ordering restrictions

There are no ordering requirements for implicit accesses to any type of memory.

Definition of program order of memory accesses

The program order of instruction execution is defined as the order of the instructions in the

control flow trace. Two explicit memory accesses in an execution can either be:

Ordered Denoted by <. If the accesses are Ordered, then they must occur strictly in

order.

Weakly Ordered Denoted by <=. If the accesses are Weakly Ordered, then they must occur

in order or simultaneously.

The rules for determining this for two accesses A1 and A2 are:

1. If A1 and A2 are generated by two different instructions, then:

• A1 < A2 if the instruction that generates A1 occurs before the instruction that

generates A2 in program order.

• A2 < A1 if the instruction that generates A2 occurs before the instruction that

generates A1 in program order.

Normal

read

Device read

Strongly

Ordered

read

Normal

write

Device write

Strongly

Ordered

write

Non-

Shared

Non-

Shared

Normal read

Strongly Ordered write

Device read, Non-Shared

Device write, Shared

Device read, Shared

Strongly Ordered read

Normal write

Device write, Non-Shared

a. The processor orders the normal read ahead of normal write.

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English

ARM ARM1176JZF-S User Manual

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