System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-131
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Table 3-132 lists how the bit values correspond with the functions of the Peripheral Port
Memory Remap Register.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-133 lists the results of attempted access for each mode.
Table 3-132 Peripheral Port Memory Remap Register bit functions
Bits Field name Function
[31:12] Base Address Gives the physical base address of the region of memory for remapping to the peripheral port.
If the processor uses the Peripheral Port Memory Remap Register while the MMU is disabled,
the virtual base address is equal to the physical base address that is used.
The assumption is that the Base Address is aligned to the size of the remapped region. Any
bits in the range [(log
2
(Region size)-1):12] are ignored.
The value is the base address. The reset value is 0.
[11:5] - UNP/SBZ
[4:0] Size Indicates the size of the memory region that the peripheral port is remapped to.
All other values are reserved:
b00000 = 0KB
a
b00011 = 4KB
b00100 = 8KB
b00101 = 16KB
b00110 = 32KB
b00111 = 64KB
b01000 = 128KB
b01001 = 256KB
b01010 = 512KB
b01011 = 1MB
b01100 = 2MB
b01101 = 4MB
b01110 = 8MB
b01111 = 16MB
b10000 = 32MB
b10001 = 64MB
b10010 = 128MB
b10011 = 256MB
b10100 = 512MB
b10101 = 1GB
b10110 = 2GB.
a. The reset value, indicating that no remapping is to take place.
Table 3-133 Results of access to the Peripheral Port Remap Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
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