System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-113
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Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. The processor can access this register in User mode if the U bit, see c11,
DMA User Accessibility Register on page 3-107, for the currently selected channel is set to 1.
Table 3-113 lists the results of attempted access for each mode.
To access the DMA Control Register set the DMA Channel Number Register to the appropriate
DMA channel and read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c11
• CRm set to c4
• Opcode_2 set to 0.
For example:
[26] UM Indicates that the permission checks are based on the DMA being in User or privileged mode.
The UM bit is provided so that the User mode can be emulated by a privileged mode process.
For a User mode process the setting of the UM bit is irrelevant and behaves as if set to 1:
0 = Transfer is a privileged transfer, reset value
1 = Transfer is a User mode transfer.
[25:20] - UNP/SBZ.
[19:8] ST Indicates the increment on the external address between each consecutive access of the DMA.
A Stride of zero, reset value, indicates that the external address is not to be incremented. This
is designed to facilitate the accessing of volatile locations such as a FIFO.
The Stride is interpreted as a positive number, or zero.
The internal address increment is not affected by the Stride, but is fixed at the transaction size.
The stride value is in bytes.
The value of the Stride must be aligned to the Transaction Size, otherwise this results in a bad
parameter error, see c11, DMA Channel Status Register on page 3-117.
[7:2] - UNP/SBZ.
[1:0] TS Indicates the size of the transactions that the DMA channel performs. This is particularly
important for Device or Strongly Ordered memory locations because it ensures that accesses
to such memory occur at their programmed size:
b00 = Byte, reset value
b01 = Halfword
b10 = Word
b11 = Doubleword, 8 bytes.
a. See c11, DMA User Accessibility Register on page 3-107.
Table 3-112 DMA Control Register bit functions (continued)
Bits Field name Function
Table 3-113 Results of access to the DMA Control Register
U bit DMA bit
Secure Privileged
Read or Write
Non-secure Privileged
Read or Write
Secure User
Read or Write
Non-secure User
Read or Write
0 0 Data Undefined exception Undefined exception Undefined exception
1 Data Data Undefined exception Undefined exception
1 0 Data Undefined exception Data Undefined exception
1 Data Data Data Data
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