Unaligned and Mixed-endian Data Access Support
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-6
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4.3 Endian support
The architectural specification of unaligned data representations is defined in terms of bytes
transferred between memory and register, regardless of bus width and bus endianness.
Little-endian data items are described using lower-case byte labeling bX…b0, byteX to byte 0,
and a pointer is always treated as pointing to the least significant byte of the addressed data.
Byte invariant, BE-8, big-endian data items are described using upper-case byte labeling
B0…BX, BYTE0 to BYTEX, and a pointer is always treated as pointing to the most significant
byte of the addressed data.
4.3.1 Load unsigned byte, endian independent
The addressed byte is loaded from memory into the low eight bits of the general-purpose register
and the upper 24 bits are zeroed, as Figure 4-1 shows.
Figure 4-1 Load unsigned byte
4.3.2 Load signed byte, endian independent
The addressed byte is loaded from the memory into the low eight bits of the general-purpose
register and the sign bit is extended into the upper 24 bits of the register as Figure 4-2 shows.
Figure 4-2 Load signed byte
In Figure 4-2, se means b, bit [7], sign extension.
4.3.3 Store byte, endian independent
The low eight bits of the general-purpose register are stored into the addressed byte in memory,
as Figure 4-3 on page 4-7 shows.
b
Memory Register
31 23 15 7 0
Address
A[31:0]
70
0 0 0 b
b
Memory Register
31 23 15 7 0
Address
A[31:0]
70
se se se b
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