System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-56
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Figure 3-31 Non-Secure Access Control Register format
Table 3-51 lists how the bit values correspond with the Non-Secure Access Control Register
functions.
31 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SBZ
D
M
A
TL
C
L
SBZ
CP13
CP12
CP11
CP10
CP9
CP8
CP7
CP6
CP5
CP4
CP3
CP2
CP1
CP0
Table 3-51 Non-Secure Access Control Register bit functions
Bits
Field
name
Function
[31:19] - Reserved.
UNP/SBZ.
[18] DMA Reserves the DMA channels and registers for the Secure world and determines the page tables, Secure
or Non-secure, to use for DMA transfers. For details, see DMA on page 7-10:
0 = DMA reserved for the Secure world only and the Secure page tables are used for DMA transfers,
reset value
1 = DMA can be used by the Non-secure world and the Non-secure page tables are used for DMA
transfers.
[17] TL Prevents operations in the Non-secure world from locking page tables in TLB lockdown entries.
The Invalidate Single Entry or Invalidate ASID match operations can match a TLB lockdown entry
but an Invalidate All operation only applies to unlocked entries:
0 = Reserve TLB Lockdown registers for Secure operation only, reset value
1 = TLB Lockdown registers available for Secure and Non-secure operation.
[16] CL Prevents operations in the Non-secure world from changing cache lockdown entries:
0 = Reserve cache lockdown registers for Secure operation only, reset value
1 = Cache lockdown registers available for Secure and Non-secure operation.
[15:14] - Reserved.
UNP/SBZ.
[13:0]
CPn
a
Determines permission to access the given coprocessor in the Non-secure world:
0 = Secure access only, reset value
1 = Secure or Non-secure access.
a. n is the coprocessor number from 0 to 13.
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