System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-62
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Table 3-58 lists the results of attempted access for each mode.
To use the Translation Table Base Control Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c2
• CRm set to c0
• Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c2, c0, 2 ; Read Translation Table Base Control Register
MCR p15, 0, <Rd>, c2, c0, 2 ; Write Translation Table Base Control Register
A translation table base register is selected like this:
• If N is set to 0, always use Translation Table Base Register 0. This is the default case at
reset. It is backwards compatible with ARMv5 and earlier processors.
• If N is set greater than 0, and bits [31:32-N] of the VA are all 0, use Translation Table Base
Register 0, otherwise use Translation Table Base Register 1. N must be in the range 0-7.
Note
The ARM1176JZF-S processor cannot page table walk from level one cache. Therefore, if C is
set to 1, to ensure coherency, you must either store page tables in Inner write-through memory
or, if in Inner write-back, you must clean the appropriate cache entries after modification so that
the mechanism for the hardware page table walks sees them.
Table 3-58 Results of access to the Translation Table Base Control Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
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