System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-37
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Table 3-29 lists the results of attempted access for each mode.
To use the Instruction Set Attributes Register 0 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c2
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c0, c2, 0 ;Read Instruction Set Attributes Register 0
c0, Instruction Set Attributes Register 1
The purpose of the Instruction Set Attributes Register 1 is to provide information about the
instruction set that the processor supports beyond the basic set.
The Instruction Set Attributes Register 1 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-22 on page 3-38 shows the bit arrangement for Instruction Set Attributes Register 1.
[19:16] - Indicates support for coprocessor instructions.
0x4
, ARM1176JZF-S processors support:
• CDP, LDC, MCR, MRC, STC
• CDP2, LDC2, MCR2, MRC2, STC2
• MCRR, MRRC
• MCRR2, MRRC2.
[15:12] - Indicates support for combined compare and branch instructions.
0x0
, no support in ARM1176JZF-S processors.
[11:8] - Indicates support for bitfield instructions.
0x0
, no support in ARM1176JZF-S processors.
[7:4] - Indicates support for bit counting instructions.
0x1
, ARM1176JZF-S processors support CLZ.
[3:0] - Indicates support for atomic load and store instructions.
0x1
, ARM1176JZF-S processors support SWP and SWPB.
Table 3-29 Results of access to the Instruction Set Attributes Register 0
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
Table 3-28 Instruction Set Attributes Register 0 bit functions (continued)
Bits Field name Function
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