ARM ARM1176JZF-S User Manual

Programmer’s Model
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-21
ID012310 Non-Confidential, Unrestricted Access
Figure 2-7 Processor core register set showing banked registers
2.9.2 The Thumb state core register set
The Thumb state core register set is a subset of the ARM state set. The programmer has direct
access to:
• eight general registers, R0–R7. For details of high register access in Thumb state see
Accessing high registers in Thumb state on page 2-22
•the PC
• a stack pointer, SP, ARM R13
•an LR, ARM R14
• the CPSR.
There are banked SPs, LRs, and SPSRs for each privileged mode. Figure 2-8 on page 2-22
shows the Thumb state core register set.
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15 (PC)
R8_fiq
R9_fiq
R10_fiq
R11_fiq
R12_fiq
R13_fiq
R14_fiq
R13_svc
R14_svc
R13_abt
R14_abt
R13_irq
R14_irq
R13_und
R14_und
CPSR SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
R13_mon
R14_mon
SPSR_mon
23 mode-specific registers (banked registers)
17 banked general-purpose registers + 6 banked status registers
33 general purpose registers7 status registers
16 general
purpose
registers + 1
status register

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English