Level One Memory System
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-15
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Table 7-5 summarizes the results of instruction accesses to TCM and the cache. This also
embodies the unexpected hit behavior for the cache that Unexpected hit behavior on page 7-6
describes. In Table 7-5, the Instruction Cache can only be hit if the memory location being
accessed is marked as being Cacheable and not shareable. A hit to the Instruction TCM refers
to hitting an address in the range covered by that TCM.
Miss Hit Miss Read from Data Cache. Write to Data Cache.
If Write-Through, write to level two.
Miss Miss Hit Read from Instruction TCM.
No cache fill even if marked
Cacheable.
Write to Instruction TCM.
No write to level two even if marked as
Write-Through.
Miss Miss Miss If Cacheable and cache
enabled, cache linefill.
If Noncacheable or cache
disabled, read to level two.
Write to level two.
a. Excludes unexpected hit.
Table 7-4 Summary of data accesses to TCM and caches (continued)
Data
TCM
Data
cache
Instruction
TCM
a
Read behavior Write behavior
Table 7-5 Summary of instruction accesses to TCM and caches
Instruction
TCM
Instruction
cache
a
Data
TCM
Read behavior
Hit Hit Don’t care Read from I TCMNo linefill to I Cache even if marked Cacheable
Hit Miss Don’t care Read from Instruction TCM.
No linefill to Instruction Cache, even if marked cacheable.
Miss Hit Don’t care Read from Instruction Cache.
Miss Miss Don’t care If Cacheable and cache enabled, cache linefill.
If Noncacheable or cache disabled, read to level two.
a. Excludes unexpected hit.
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