Signal Descriptions
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-6
ID012310 Non-Confidential, Unrestricted Access
A.4 Interrupt signals, including VIC interface
Table A-4 lists the interrupt signals, including those used with the VIC interface.
Note
All the outputs listed in this section have their reset values in Standby mode.
Table A-4 Interrupt signals
Name Direction Description
INTSYNCEN Input When HIGH, indicates that the internal nFIQ and nIRQ
synchronizers are bypassed and the interface is synchronous
IRQACK Output Interrupt acknowledge
IRQADDR[31:2] Input Address of IRQ
IRQADDRV Input Indicates IRQADDR is valid
IRQADDRVSYNCEN Input When HIGH, indicates that IRQADDRV synchronizer is
bypassed and the interface is synchronous
nFIQ
a
a. Because this signal is level-sensitive, to generate an interrupt you must ensure it is held LOW until the
processor sends a suitable interrupt response.
Input Fast interrupt request
nIRQ
a
Input Interrupt request
nPMUIRQ Output Interrupt request from System Metrics
nDMAIRQ Output Non-secure DMA Interrupt
nDMASIRQ Output Secure DMA Interrupt
nDMAEXTERRIRQ Output Not maskable error DMA Interrupt
To Next Page
Loading...
Need help?
General
