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Introduction

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1.11 Product revisions

This section describes differences in functionality between product revisions of the

ARM1176JZF-S processor:

r0p0-r0p1 Contains the following differences:

• The addition of the CPUCLAMP input in r0p1 to better support IEM. See

Intelligent Energy Management on page 10-7.

• The top level RTL hierarchy has been changed in r0p1 to better support

IEM. See Intelligent Energy Management on page 10-7.

• The architectural clock gating scheme for the generation of clock dedicated

to the RAMs has been changed. For more information see the description

of the RAM interface implementation in the ARM1176JZF-S

™

and

ARM1176JZ-S

™

Implementation Guide.

r0p1-r0p2 There are no functional differences between r0p1 and r0p2.

r0p2-r0p4 There are no functional differences between r0p2 and r0p4.

r0p4-r0p6 Between r0p4 and r0p6 there are no differences in the functionality described in

this Technical Reference Manual. However, r0p6 introduces optional top-level

latches, for implementing Dormant mode or IEM with cell libraries that do not

provide retention latches. For more information see the description of Dormant

mode implementation in the ARM1176JZF-S

™

and ARM1176JZ-S

™

Implementation Guide.

r0p6-r0p7 There are no functional differences between r0p6 and r0p7.

Note

Product revisions r0p3 and r0p5 were not generally available.

ARM ARM1176JZF-S User Manual

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