ARM ARM1176JZF-S - Page 72

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-46
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Signed halfword LDRSH <Rd>, [<Rn>, <Rm>]
Byte LDRB <Rd>, [<Rn>, <Rm>]
Signed byte LDRSB <Rd>, [<Rn>, <Rm>]
PC-relative LDR <Rd>, [PC, #<immed_8*4>]
SP-relative LDR <Rd>, [SP, #<immed_8*4>]
Multiple LDMIA <Rn>!, <reglist>
Store With immediate offset -
Word
STR <Rd>, [<Rn>, #<immed_5*4>]
Halfword STRH <Rd>, [<Rn>, #<immed_5*2>]
Byte STRB <Rd>, [<Rn>, #<immed_5>]
With register offset -
Word
STR <Rd>, [<Rn>, <Rm>]
Halfword STRH <Rd>, [<Rn>, <Rm>]
Byte STRB <Rd>, [<Rn>, <Rm>]
SP-relative STR <Rd>, [SP, #<immed_8*4>]
Multiple STMIA <Rn>!, <reglist>
Push/Pop Push registers onto stack PUSH <reglist>
Push LR and registers onto stack PUSH <reglist, LR>
Pop registers from stack POP <reglist>
Pop registers and PC from stack POP <reglist, PC>
Change state Change processor state CPS <effect> <iflags>
Change endianness SETEND <endian_specifier>
Byte-reverse Byte-reverse word REV <Rd>, <Rm>
Byte-reverse halfword REV16 <Rd>, <Rm>
Byte-reverse signed halfword REVSH <Rd>, <Rm>
Supervisor call SVC <immed_8>
Software breakpoint BKPT <immed_8>
Sign or zero extend Sign extend 16 to 32 SXTH<Rd>, <Rm>
Sign extend 8 to 32 SXTB<Rd>, <Rm>
Zero extend 16 to 32 UXTH<Rd>, <Rm>
Zero extend 8 to 32 UXTB<Rd>, <Rm>
Table 1-16 Thumb instruction set summary (continued)
Operation Assembler