ARM ARM1176JZF-S - Page 71

Introduction
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-45
ID012310 Non-Confidential, Unrestricted Access
Negate NEG <Rd>, <Rm>
Multiply MUL <Rd>, <Rm>
Compare Compare immediate CMP <Rn>, #<immed_8>
Compare LowReg and LowReg, update flags CMP <Rn>, <Rm>
Compare LowReg and HighReg, update flags CMP <Rn>, <Rm>
Compare HighReg and LowReg, update flags CMP <Rn>, <Rm>
Compare HighReg and HighReg, update flags CMP <Rn>, <Rm>
Compare negative CMN <Rn>, <Rm>
Logical AND AND <Rd>, <Rm>
XOR EOR <Rd>, <Rm>
OR ORR <Rd>, <Rm>
Bit clear BIC <Rd>, <Rm>
Move NOT MVN <Rd>, <Rm>
Test bits TST <Rd>, <Rm>
Shift/Rotate Logical shift left LSL <Rd>, <Rm>, #<immed_5>
LSL <Rd>, <Rs>
Logical shift right LSR <Rd>, <Rm>, #<immed_5>
LSR <Rd>, <Rs>
Arithmetic shift right ASR <Rd>, <Rm>, #<immed_5>
ASR <Rd>, <Rs>
Rotate right ROR <Rd>, <Rs>
Branch Conditional B{cond} <label>
Unconditional B <label>
Branch with link BL <label>
Branch, link and exchange BLX <label>
Branch, link and exchange BLX <Rm>
Branch and exchange BX <Rm>
Load With immediate offset -
Word
LDR <Rd>, [<Rn>, #<immed_5*4>]
Halfword LDRH <Rd>, [<Rn>, #<immed_5*2>]
Byte LDRB <Rd>, [<Rn>, #<immed_5>]
With register offset -
Word
LDR <Rd>, [<Rn>, <Rm>]
Halfword LDRH <Rd>, [<Rn>, <Rm>]
Table 1-16 Thumb instruction set summary (continued)
Operation Assembler