ARM ARM1176JZF-S User Manual

Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
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• Stop Prefetch Range operations
• Read Block Transfer Status Register operations.
The ARM1176JZF-S processor implements all the other block transfer operations:
• Invalidate Cache Range, Instruction and Data
• Clean Data Cache Range
• Clean and Invalidate Data Cache Range.
B.2.7 Tightly-Coupled Memories
The ARM1136JF-S processor implements zero or one Tightly Coupled Memories on each side,
Instruction and Data. The possible TCM sizes for ARM1136JF-S for each side are:
•0KB
•4KB
•8KB
• 16KB
• 32KB
• 64KB.
The ARM1176JZF-S processor implements zero, one or two Tightly Coupled Memories on
each side. For each side, the two TCMs are physically located within one RAM. Table B-1 lists
the possible configurations for ARM1176JZF-S Tightly-Coupled Memories for each side:
B.2.8 Fault Address Register
ARM1136JF-S processors includes an Instruction Fault Address Register in the system control
coprocessor, CP15, with the encoding:
• Opcode_1 = 0
•Crn = 6
•Crm = 0
• Opcode_2 = 1.
The ARM1136JF-S IFAR is only updated on watchpoints.
The ARM1136JF-S IFAR is the Watchpoint Fault Address Register in ARM1176JZF-S
processors. The WFAR is in the CP14 coprocessor with the encoding:
• Opcode_1 = 0
•Crn = 0
•Crm = 6
• Opcode_2 = 0.
Table B-1 TCM for ARM1176JZF-S processors
Number of TCM TCM size RAM size
00 KB0 KB
14 KB4 KB
24 KB8 KB
2 8 KB 16 KB
2 16 KB 32 KB
2 32 KB 64 KB

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English