System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-38
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Figure 3-22 Instruction Set Attributes Register 1 format
Table 3-30 lists how the bit values correspond with the Instruction Set Attributes Register 1
functions.
Table 3-31 lists the results of attempted access for each mode.
To use the Instruction Set Attributes Register 1 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c2
• Opcode_2 set to 1.
- - - - - --
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
-
Table 3-30 Instruction Set Attributes Register 1 bit functions
Bits Field name Function
[31:28] - Indicates support for Java instructions.
0x1
, ARM1176JZF-S processors support BXJ and J bit in PSRs.
[27:24] - Indicates support for interworking instructions.
0x2
, ARM1176JZF-S processors support:
• BX, and T bit in PSRs
• BLX, and PC loads have BX behavior.
[23:20] - Indicates support for immediate instructions.
0x0
, no support in ARM1176JZF-S processors.
[19:16] - Indicates support for if then instructions.
0x0
, no support in ARM1176JZF-S processors.
[15:12] - Indicates support for sign or zero extend instructions.
0x2
, ARM1176JZF-S processors support:
• SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH
• SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH.
[11:8] - Indicates support for exception 2 instructions.
0x1
, ARM1176JZF-S processors support SRS, RFE, and CPS.
[7:4] - Indicates support for exception 1 instructions.
0x1
, ARM1176JZF-S processors support LDM(2), LDM(3) and STM(2).
[3:0] - Indicates support for endianness control instructions.
0x1
, ARM1176JZF-S processors support SETEND and E bit in PSRs.
Table 3-31 Results of access to the Instruction Set Attributes Register 1
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
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