Debug Test Access Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-6
ID012310 Non-Confidential, Unrestricted Access
14.5 The DBGTAP port and debug registers
The processor DBGTAP controller is the part of the debug unit that enables access through the
DBGTAP to the on-chip debug resources, such as breakpoint and watchpoint registers. The
DBGTAP controller is based on the IEEE 1149.1 standard and supports:
• a device ID register
• a bypass register
• a five-bit instruction register
• a five-bit scan chain select register.
In addition, the public instructions that Table 14-1 lists are supported.
Table 14-1 Supported public instructions
Binary code Instruction Description
b00000 EXTEST This instruction connects the selected scan chain between DBGTDI and DBGTDO.
When the instruction register is loaded with the EXTEST instruction, the debug scan
chains can be written. See Scan chains on page 14-10.
b00001 - Reserved.
b00010 Scan_N Selects the Scan Chain Select Register (SCREG). This instruction connects SCREG
between DBGTDI and DBGTDO. See Scan chain select register (SCREG) on
page 14-9.
b00011 - Reserved.
b00100 Restart Forces the processor to leave Debug state. This instruction is used to exit from Debug
state. The processor restarts when the Run-Test/Idle state is entered.
b00101 - Reserved.
b00110 - Reserved.
b00111 - Reserved.
b01000 Halt Forces the processor to enter Debug state. This instruction stops the processor and puts
it into Debug state.
b01001 - Reserved.
b01010-b01011 - Reserved.
b01100 INTEST This instruction connects the selected scan chain between DBGTDI and DBGTDO.
When the instruction register is loaded with the INTEST instruction, the debug scan
chains can be read. See Scan chains on page 14-10.
b01101-b11100 - Reserved.
To Next Page
Loading...
Need help?
General
