System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-45
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Operation of the Control Register
Table 3-39 lists how the bit values correspond with the Control Register functions.
Table 3-39 Control Register bit functions
Bits
Field
name
Access Function
[31:30] - - This field is UNP when read. Write as the existing value.
[29] FA Banked This bit controls the Force AP functionality in the MMU that generates Access Bit
faults, see Access permissions on page 6-11
0 = Force AP is disabled, reset value.
1 = Force AP is enabled.
[28] TR Banked This bit controls the TEX remap functionality in the MMU, see Memory region
attributes on page 6-14.
0 = TEX remap disabled. Normal ARMv6 behavior, reset value
1 = TEX remap enabled. TEX[2:1] become page table bits for OS.
[27:26] - - This field is UNP when read. Write as the existing value.
[25] EE bit Banked Determines how the E bit in the CPSR bit is set on an exception. The reset value
depends on external signals.
0 = CPSR E bit is set to 0 on an exception, reset value.
1 = CPSR E bit is set to 1 on an exception.
[24] VE bit Banked Enables the VIC interface to determine interrupt vectors.
See the description of the V bit, bit [13].
0 = Interrupt vectors are fixed, reset value.
1 = Interrupt vectors are defined by the VIC interface.
[23] XP bit Banked Enables the extended page tables to be configured for the hardware page translation
mechanism.
0 = Subpage AP bits enabled, reset value.
1 = Subpage AP bits disabled.
[22] U bit Banked Enables unaligned data access operations, including support for mixed little-endian and
big-endian operation. The A bit has priority over the U bit. The reset value of the U bit
depends on external signals.
0 = Unaligned data access support disabled, reset value. The processor treats unaligned
loads as rotated aligned data accesses.
1 = Unaligned data access support enabled. The processor permits unaligned loads and
stores and support for mixed endian data is enabled.
[21] FI bit Secure
modify
only
Configures low latency features for fast interrupts. This bit is overridden by the FIO bit,
see c1, Auxiliary Control Register on page 3-48.
0 = All performance features enabled, reset value.
1 = Low interrupt latency configuration enabled. See Low interrupt latency
configuration on page 2-40.
[20:19] - - UNP/SBZ
[18] IT bit - Deprecated. Global enable for instruction TCM.
Function redundant in ARMv6.
SBO
[17] - - UNP/SBZ
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