ARM ARM1176JZF-S User Manual

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-46
ID012310 Non-Confidential, Unrestricted Access
[16] DT bit - Deprecated. Global enable for data TCM.
Function redundant in ARMv6.
SBO
[15] L4 bit Secure
modify
only
Determines if the T bit is set for PC load instructions. For more details see the ARM
Architecture Reference Manual.
0 = Loads to PC set the T bit, reset value.
1 = Loads to PC do not set the T bit, ARMv4 behavior.
[14] RR bit Secure
modify
only
Determines the replacement strategy for the cache.
0 = Normal replacement strategy by random replacement, reset value.
1 = Predictable replacement strategy by round-robin replacement.
[13] V bit Banked Determines the location of exception vectors, see c12, Secure or Non-secure Vector
Base Address Register on page 3-121 and c12, Monitor Vector Base Address Register
on page 3-122. The reset value of the V bit depends on an external signal.
0 = Normal exception vectors selected, the Vector Base Address Registers determine
the address range, reset value.
1 = High exception vectors selected, address range =
0xFFFF0000-0xFFFF001C .
[12] I bit Banked Enables level one instruction cache.
0 = Instruction Cache disabled, reset value.
1 = Instruction Cache enabled.
[11] Z bit Banked Enables branch prediction.
0 = Program flow prediction disabled, reset value.
1 = Program flow prediction enabled.
[10] F bit - Should Be Zero
[9] R bit Banked Deprecated. Enables ROM protection. If you modify the R bit this does not affect the
access permissions of entries already in the TLB. See MMU software-accessible
registers on page 6-53.
0 = ROM protection disabled, reset value.
1 = ROM protection enabled.
[8] S bit Banked Deprecated. Enables MMU protection. If you modify the S bit this does not affect the
access permissions of entries already in TLB.
0 = MMU protection disabled, reset value.
1 = MMU protection enabled.
[7] B bit Secure
modify
only
Determines operation as little-endian or big-endian word invariant memory system and
the names of the low four-byte addresses within a 32-bit word. The reset value of the B
bit depends on the BIGENDINIT external signal.
0 = Little-endian memory system, reset value.
1 = Big-endian word-invariant memory system.
[6:4] - - This field returns 1 when read.
Should Be One.
[3] W bit - Not implemented in the processor.
Read As One
Write Ignore.
Table 3-39 Control Register bit functions (continued)
Bits
Field
name
Access Function

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English