Debug Test Access Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-8
ID012310 Non-Confidential, Unrestricted Access
14.6 Debug registers
You can connect the following debug registers between DBGTDI and DBGTDO:
• Bypass register
• Device ID code register
• Instruction register on page 14-9
• Scan chain select register (SCREG) on page 14-9
• Scan chain 0, debug ID register (DIDR) on page 14-11
• Scan chain 1, Debug Status and Control Register (DSCR) on page 14-11
• Scan chain 4, instruction transfer register (ITR) on page 14-13
• Scan chain 5 on page 14-15.
• Scan chain 6 on page 14-17.
• Scan chain 7 on page 14-17.
14.6.1 Bypass register
Purpose Bypasses the device by providing a path between DBGTDI and
DBGTDO.
Length 1 bit.
Operating mode When the bypass instruction is the current instruction in the instruction
register, serial data is transferred from DBGTDI to DBGTDO in the
Shift-DR state with a delay of one TCK cycle. There is no parallel output
from the bypass register. A logic 0 is loaded from the parallel input of the
bypass register in the Capture-DR state. Nothing happens at the
Update-DR state.
Order Figure 14-3 shows the order of bits in the bypass register.
Figure 14-3 Bypass register bit order
14.6.2 Device ID code register
Purpose Device identification. To distinguish the ARM1176JZF-S processors from
other processors, the DBGTAP controller ID is unique for each. This
means that a DBGTAP debugger, such as RealView ICE, can easily see the
processor that it is connected to. The Device ID register version and
manufacturer ID fields are routed to the edge of the chip so that partners
can create their own Device ID numbers by tying the pins to HIGH or
LOW values.
The default manufacturer ID for the ARM1176JZF-S processor is
b11110000111. The part number field is hard-wired inside the
ARM1176JZF-S to
0x7B76
.
0b0
DBGTDI DBGTDO
Bypass
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