ARM ARM1176JZF-S - Branches; Table 16-11 Branch Instruction Cycle Timing Behavior

Cycle Timings and Interlock Behavior
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-14
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16.8 Branches
This section describes the cycle timing behavior for the B, BL, and BLX instructions.
Branches are subject to dynamic, static and return stack predictions. Table 16-11 lists example
branch instructions and their cycle timing behavior.
Table 16-11 Branch instruction cycle timing behavior
Example instruction
Cycle
s
Comment
B <immed> 0 Folded dynamic prediction
B<immed>, BL<immed>, BLX<immed> 1 Not-folded dynamic prediction
B<immed>, BL<immed>, BLX<immed> 1 Correct not-taken static prediction
B<immed>, BL<immed>, BLX<immed> 4 Correct taken static prediction
B<immed>, BL<immed>, BLX<immed>
5-7
a
a. Mispredicted branches, including taken unpredicted branches, takes a varying
number of cycles to execute depending on their distance from a flag setting
instruction. The timing behavior is:
Cycle = MAX (MaxCycles - FlagCycleDistance, MinCycles).
Incorrect dynamic/static prediction
BX R14 4 Correct return stack prediction
BX R14 7 Incorrect return stack prediction
BX R14 5 Empty return stack
BX <cond> R14
5-7
a
Conditional return
BX <cond> <reg> , BLX <cond> <reg> 1 If not taken
BX <cond> <reg> , BLX <cond> <reg>
5-7
a
If taken