Debug
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-32
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13.8 Debug events
A debug event is any of the following:
• Software debug event
• External debug request signal
• Halt DBGTAP instruction on page 13-33.
13.8.1 Software debug event
A software debug event is any of the following:
• A watchpoint debug event. This occurs when:
— the DMVA present in the data bus matches the watchpoint value
— all the conditions of the WCR match
— the watchpoint is enabled
— the linked contextID-holding BRP, if any, is enabled and its value matches the
context ID in CP15 c13.
• A breakpoint debug event. This occurs when:
— an instruction was fetched and the IMVA present in the instruction bus matched or
mismatched the breakpoint value, according to the meaning field in the BCR
— at the same time the instruction was fetched, all the conditions of the BCR matched
— the breakpoint was enabled
— at the same time the instruction was fetched, the linked contextID-holding BRP, if
any, was enabled and its value matched the context ID in CP15 c13
— the instruction is now committed for execution.
• A breakpoint debug event also occurs when:
— an instruction was fetched and the CP15 Context ID, register 13, matched the
breakpoint value
— at the same time the instruction was fetched, all the conditions of the BCR matched
— the breakpoint was enabled
— the instruction is now committed for execution.
• A software breakpoint debug event. This occurs when a BKPT instruction is committed
for execution.
• A vector catch debug event. This occurs when:
— The instruction at a vector location was fetched in the appropriate Secure or
Non-secure world. This includes any kind of prefetches, not only the ones because
of exception entry.
— At the same time the instruction was fetched, the corresponding bit of the VCR was
set, vector catch enabled.
— The instruction is now committed for execution.
13.8.2 External debug request signal
The processor has an external debug request input signal, EDBGRQ. When this signal is HIGH
it causes the processor to enter Debug state when execution of the current instruction has
completed. When this happens, the DSCR[5:2] method of entry bits are set to b0100.This signal
can be driven by the ETM to signal a trigger to the core. For example, if a memory permission
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