Signal Descriptions
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-9
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A.5.3 Peripheral port signals
The peripheral port is a 32-bit wide read/write AXI port. The standard AXI read channel, write
channel, and write response channel signal names are suffixed with P, and the implementation
details of the port are:
• AWID[3:0], WID[3:0], BID[3:0], ARID[3:0], and RID[3:0] signals are not
implemented
• the write data bus is implemented as WDATAP[31:0], and therefore the write strobe
signal is implemented as WSTRBP[3:0]
Table A-7 Data port AXI signal implementation
Name Direction Type Description
AWSIZERW[2:0] Output Write Write burst size:
000, 8-bit transfers
001, 16-bit transfers
010, 32-bit transfers
011, 64-bit transfers, maximum for the data port.
AWBURSTRW[1:0] Output Write Write burst type:
01, INCR Incrementing burst
10, WRAP Wrapping burst.
AWLOCKRW[1:0] Output Write Write lock type:
00, Normal access
01, Exclusive access.
ARLENRW[3:0] Output Read Burst length that gives the exact number of transfer:
b0000, 1 data transfer
b0001, 2 data transfers
b0010, 3 data transfers
b0011, 4 data transfers
b0100, 5 data transfers
b0101, 6 data transfers
b0110, 7 data transfers.
ARSIZERW[2:0] Output Read Burst size:
b000, indicating 8-bit transfer
b001, indicating 16-bit transfer
b010, indicating 32-bit transfer
b011, indicating 64-bit transfer.
ARBURSTRW[1:0] Output Read Burst type:
b01, INCR, Incrementing burst
b10, WRAP, Wrapping burst.
ARSIDEBANDRW[4:0] Output Read Indicates read accesses to shared and inner cacheable memory.
AWSIDEBANDRW[4:0] Output Write Indicates write accesses to shared and inner cacheable memory.
WRITEBACK Output - Indicates that the current transaction is a cache line eviction. This
signal has the same timing as the write address channel signals.
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