System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-68
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Note
When the SCR EA bit is set, see c1, Secure Configuration Register on page 3-52, the processor
writes to the Secure Instruction Fault Status Register on a Secure Monitor entry caused by an
external abort.
To use the IFSR read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c5
• CRm set to c0
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c5, c0, 1 ; Read Instruction Fault Status Register
MCR p15, 0, <Rd>, c5, c0, 1 ; Write Instruction Fault Status Register
3.2.19 c6, Fault Address Register
The purpose of the Fault Address Register (FAR) is to hold the Modified Virtual Address (MVA)
of the fault when a precise abort occurs.
The FAR is:
•in CP15 c6
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
The Fault Address Register bits [31:0] contain the MVA that the precise abort occurred on. The
reset value is 0.
Table 3-65 lists the results of attempted access for each mode.
To use the FAR read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c6
• CRm set to c0
• Opcode_2 set to 0.
For example:
MRC p15, 0, <Rd>, c6, c0, 0 ; Read Fault Address Register
MCR p15, 0, <Rd>, c6, c0, 0 ; Write Fault Address Register
A write to this register sets the FAR to the value of the data written. This is useful for a debugger
to restore the value of the FAR.
The ARM1176JZF-S processor also updates the FAR on debug exception entry because of
watchpoints, see Effect of a debug event on CP15 registers on page 13-34 for more details.
Table 3-65 Results of access to the Fault Address Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
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