System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-28
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Figure 3-15 Processor Feature Register 1 format
Table 3-14 lists how the bit values correspond with the Processor Feature Register 1 functions.
Table 3-15 lists the results of attempted access for each mode.
To use the Processor Feature Register 1 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c0, c1, 1 ;Read Processor Feature Register 1
ReservedReservedReservedReservedReserved
31 8 7 4 3 016 15 12 1128 27 24 23 20 19
Microcontroller programmer's model
Security extension
Programmer's model
Table 3-14 Processor Feature Register 1 bit functions
Bits Field name Function
[31:28] - Reserved. RAZ
[27:24] - Reserved. RAZ.
[23:20] - Reserved. RAZ.
[19:16] - Reserved. RAZ.
[15:12] - Reserved. RAZ.
[11:8] Microcontroller programmer’s model Indicates support for the ARM microcontroller programmer’s model.
0x0
, Not supported by ARM1176JZF-S processors.
[7:4] Security extension Indicates support for Security Extensions Architecture v1.
0x1
, ARM1176JZF-S processors support Security Extensions
Architecture v1, TrustZone.
[3:0] Programmer’s model Indicates support for standard ARMv4 programmer’s model.
0x1
, ARM1176JZF-S processors support the ARMv4 model.
Table 3-15 Results of access to the Processor Feature Register 1
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Undefined exception Data Undefined exception Undefined exception
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