ARM ARM1176JZF-S User Manual

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-50
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Table 3-43 lists the results of attempted access for each mode.
To use the Auxiliary Control Register you must use a read modify write technique. To access
the Auxiliary Control Register read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c1
• CRm set to c0
• Opcode_2 set to 1.
For example:
MRC p15, 0, <Rd>, c1, c0, 1 ; Read Auxiliary Control Register
MCR p15, 0, <Rd>, c1, c0, 1 ; Write Auxiliary Control Register
[4] RA Disables clean entire data cache:
0 = Clean entire data cache enabled, reset value
1 = Clean entire data cache disabled.
[3] TR Enables MicroTLB random replacement strategy. This depends on the cache replacement strategy that
the RR bit controls, see c1, Control Register on page 3-44. The MicroTLB strategy is only random
when the cache strategy is random:
0 = MicroTLB replacement is Round Robin, reset value
1 = MicroTLB replacement is Random if cache replacement is also Random.
[2] SB Enables static branch prediction. This depends on program flow prediction that the Z bit enables, see
c1, Control Register on page 3-44:
0 = Static branch prediction disabled
1 = Static branch prediction enabled, if the Z bit is set. The reset value is 1.
[1] DB Enables dynamic branch prediction. This depends on program flow prediction that the Z bit enables,
see c1, Control Register on page 3-44:
0 = Dynamic branch prediction disabled
1 = Dynamic branch prediction enabled, if the Z bit is set. The reset value is 1.
[0] RS Enables the return stack. This depends on program flow prediction that the Z bit enables, see c1,
Control Register on page 3-44:
0 = Return stack is disabled
1 = Return stack is enabled, if the Z bit is set. The reset value is 1.
Table 3-42 Auxiliary Control Register bit functions (continued)
Bits
Field
name
Function
Table 3-43 Results of access to the Auxiliary Control Register
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Data Data Data Undefined exception Undefined exception

ARM ARM1176JZF-S Specifications

General

Brand	ARM
Model	ARM1176JZF-S
Category	Computer Hardware
Language	English