ARM ARM1176JZF-S - Figure 3-18 Memory Model Feature Register 1 Format; Table 3-22 Memory Model Feature Register 1 Bit Functions

System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-32
ID012310 Non-Confidential, Unrestricted Access
To use the Memory Model Feature Register 0 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 4.
For example:
MRC p15, 0, <Rd>, c0, c1, 4 ;Read Memory Model Feature Register 0.
c0, Memory Model Feature Register 1
The purpose of the Memory Model Feature Register 1 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 1 is:
•in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-18 shows the bit arrangement for Memory Model Feature Register 1.
Figure 3-18 Memory Model Feature Register 1 format
Table 3-22 lists how the bit values correspond with the Memory Model Feature Register 1
functions.
- - - - - --
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0
-
Table 3-22 Memory Model Feature Register 1 bit functions
Bits
Field
name
Function
[31:28] - Indicates support for branch target buffer.
0x1 , ARM1176JZF-S processors require flushing of branch predictor on VA change.
[27:24] - Indicates support for test and clean operations on data cache, Harvard or unified architecture.
0x0 , no support in ARM1176JZF-S processors.
[23:20] - Indicates support for level one cache, all maintenance operations, unified architecture.
0x0 , no support in ARM1176JZF-S processors.
[19:16] - Indicates support for level one cache, all maintenance operations, Harvard architecture.
0x3 , ARM1176JZF-S processors support:
• invalidate instruction cache including branch prediction
• invalidate data cache
• invalidate instruction and data cache including branch prediction
• clean data cache, recursive model using cache dirty status bit
• clean and invalidate data cache, recursive model using cache dirty status bit.
[15:12] - Indicates support for level one cache line maintenance operations by Set/Way, unified architecture.
0x0 , no support in ARM1176JZF-S processors.