System Control Coprocessor
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-104
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Table 3-102 lists the encoding for the Inner or Outer cacheable attribute bit fields I0 to I7 and
O0 to O7.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-103 lists the results of attempted access for each mode.
To use the memory region remap registers read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c10
• CRm set to c2
[13:12] - Remaps Inner attribute for {TEX[0],C,B} = b110
b00 = reset value
[11:10] - Remaps Inner attribute for {TEX[0],C,B} = b101
b10 = reset value
[9:8] - Remaps Inner attribute for {TEX[0],C,B} = b100
b00 = reset value
[7:6] - Remaps Inner attribute for {TEX[0],C,B} = b011
b11 = reset value
[5:4] - Remaps Inner attribute for {TEX[0],C,B} = b010
b10 = reset value
[3:2] - Remaps Inner attribute for {TEX[0],C,B} = b001
b00 = reset value
[1:0] - Remaps Inner attribute for {TEX[0],C,B} = b000
b00 = reset value
a. The reset values ensure that no remapping occurs at reset.
Table 3-102 Remap encoding for Inner or Outer cacheable attributes
Encoding Cacheable attribute
b00 Noncacheable
b01 Write-back, allocate on write
b10 Write-through, no allocate on write
b11 Write-back, no allocate on write
Table 3-103 Results of access to the memory region remap registers
Secure Privileged Non-secure Privileged
User
Read Write Read Write
Secure data Secure data Non-secure data Non-secure data Undefined exception
Table 3-101 Normal Memory Remap Register bit functions (continued)
Bits Field name
Function
a
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