Clocking and Resets
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9.4 Reset modes
The reset signals present in the processor design enable you to reset different parts of the design
independently. Table 9-1 lists the reset signals, and the combinations and possible applications
that you can use them in.
If you do not use VFP shutdown for power saving, you can treat the nVFPRESETIN signal in
the same way as nRESETIN. For more information on power management and VFP, see VFP
shutdown on page 10-6.
9.4.1 Power-on reset
You must apply power-on or cold reset to the processor when power is first applied to the
system. In the case of power-on reset, the leading, falling, edge of the reset signals, nRESETIN
and nPORESETIN, does not have to be synchronous to CLKIN. Because the nRESETIN and
nPORESETIN signals are synchronized within the processor, you do not have to synchronize
these signals. Figure 9-6 shows the application of power-on reset.
Figure 9-6 Power-on reset
It is recommended that you assert the reset signals for at least three CLKIN cycles to ensure
correct reset behavior. Adopting a three-cycle reset eases the integration of other ARM parts into
the system, for example, ARM9TDMI-based designs.
It is not necessary to assert DBGnTRST on power-up.
9.4.2 CP14 debug logic
Because the nPORESETIN signal is synchronized within the processor, you do not have to
synchronize this signal.
Table 9-1 Reset modes
Reset mode nRESETIN DBGnTRST nPORESETIN Application
Power-on reset 0 x 0 Reset at power up, full system reset.
Hard reset or cold reset.
Processor reset 0 x 1 Reset of processor core only, watchdog
reset.
Soft reset or warm reset.
DBGTAP reset 1 0 1 Reset of DBGTAP logic.
Normal 1 x 1 No reset. Normal run mode.
CLKIN
nRESETIN
nPORESETIN
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