ARM ARM1176JZF-S - Interrupt Entry Flowchart; Figure 12-3 Interrupt Entry Sequence

Vectored Interrupt Controller Port
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 12-7
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12.4 Interrupt entry flowchart
Figure 12-3.shows all the decisions and actions required to complete interrupt entry. For more
information on interrupt entry, see Exception vectors on page 2-48.
Figure 12-3 Interrupt entry sequence
!((nFIQ||F)
&&(nIRQ||I))
TRUE
!(nFIQ||F) VE==1
TRUE
Take IRQACK
HIGH
LR_irq =
RA+4
SPSR_irq =
CPSR
CPSR[4:0] =
IRQ mode
CPSR[5] =
ARM state
CPSR[7] =
IRQs disabled
VE==1
FALSE
V==1
LR_fiq =
RA+4
CPSR[4:0] =
FIQ mode
CPSR[5] =
ARM state
CPSR[7] =
FIQs and IRQs
disabled
SPSR_fiq =
CPSR
V==1
PC[31:0] =
0xFFFF0018
TRUE
PC[31:0] =
IRQADDR[31:2],
0b00
PC[31:0] =
NSBA + 0x1C
FALSE
PC[31:0] =
0xFFFF001C
TRUE
!(IRQADDRV
&& VE)
!IRQ
ADDRV==1
TRUE
TRUE
FALSE
FIQ = 1 in
SCR?
LR_mon =
RA+4
CPSR[4:0] =
MON mode
CPSR[5] =
ARM state
CPSR[7] =
FIQs and IRQs
disabled
SPSR_mon =
CPSR
TRUE
PC[31:0] =
MBA + 0x1C
IRQ = 1 in
SCR?
LR_mon =
RA+4
CPSR[4:0] =
MON mode
CPSR[5] =
ARM state
CPSR[7] =
IRQs disabled
SPSR_mon =
CPSR
TRUE
PC[31:0] =
MBA + 0x18
FALSE
FALSE
Secure
state?
FALSE
PC[31:0] =
SBA + 0x1C
TRUE
PC[31:0] =
NSBA + 0x18
FALSE
Secure
state?
FALSE
PC[31:0] =
SBA + 0x18
TRUE
TRUE
TRUE
FALSE
FALSE
FALSE
FALSE