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Vectored Interrupt Controller Port

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The clearing of the interrupt is handled in software by the interrupt handling routine. This

enables multiple interrupt sources to share a single interrupt priority. In addition, the interrupt

handling routine must communicate to the VIC that the interrupt currently being handled is

complete, using the memory-mapped or coprocessor-mapped interface, to enable the interrupt

masking to be unwound.

12.3.1 PL192 VIC timing

As its part of the handshake mechanism, the PL192 VIC:

1. Synchronizes IRQACK on its way in if the peripheral port clocking mode is

asynchronous or bypasses the synchronizers if it is in synchronous mode.

2. Asserts IRQADDRV when an address is ready at IRQADDR, and holds that address

until IRQACK is sampled LOW, even if higher priority interrupts come along.

3. Stacks the priority that corresponds to the vector address present at IRQADDR when it

samples the IRQACK signal LOW, while IRQADDRV is HIGH.

4. Clears IRQADDRV so the processor can recognize another interrupt. If nIRQ is also to

be deasserted at this point because there are no higher priority interrupts pending, it is

deasserted before or at the same time as IRQADDRV to ensure that the processor does

not take the same interrupt again.

12.3.2 Core timing

As its part of the handshake mechanism, the core:

1. Starts an interrupt entry sequence when it samples the nIRQ signal asserted.

2. Determines if an FIQ or an IRQ is going to be taken. This happens after the interrupt entry

sequence is started. If it decides that an IRQ is going to be taken, it starts the VIC port

handshake by asserting IRQACK. If it decides that the interrupt is an FIQ, then it does

not assert IRQACK and the VIC port handshake is not initiated.

3. Ignores the value of the nFIQ input until the IRQ interrupt entry sequence is completed

if it has decided that the interrupt is an IRQ.

4. Samples the IRQADDR input bus when both IRQACK and IRQADDRV are sampled

asserted. The interrupt entry sequence proceeds with this value of IRQADDR.

5. Ignores the nIRQ signal while IRQADDRV is HIGH. This gives the VIC time to deassert

the nIRQ signal if there is no higher priority interrupt pending.

6. Ignores the nFIQ signal while IRQADDRV is HIGH.

ARM ARM1176JZF-S User Manual

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