Debug
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-31
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13.7 Changing the debug enable signals
The behavior of these control signals, DBGEN, SPIDEN, and SPNIDEN, is primarily a
concern of the external debug interface. It is recommended that these signals do not change.
However, the architecture permits these signals to change when the processor is running or when
the processor is in Debug state.
If software running on the processor changes the state of one of these signals, before performing
debug or analysis operations that rely on the new value it must:
1. Execute the device specific sequence of instructions to change the signal value. For
instance, the software might have to write a value to a control register in a system
peripheral.
2. Perform a Data Memory Barrier operation. This stage can be omitted if the previous stage
does not involve any memory operations.
3. Poll debug registers for the view that the processor has of the signal values. This stage is
required because system specific issues might result in the processor not receiving a signal
change until some cycles after the Data Memory Barrier completes.
4. Issue an Instruction Memory Barrier sequence.
The same rules apply for instructions executed through the ITR when in Debug state.
The view that the processor has of the SPIDEN and SPNIDEN signals can be polled through
the DSCR. The processor has no register that shows its view of DBGEN. However, if DBGEN
is LOW, DSCR[15:14] read as zero, and therefore the view that the processor has of DBGEN
can be polled by writing to DSCR[15:14] and using the value read back to determine its setting.
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