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VFP Instruction Execution

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Table 21-7 lists the VFP11 pipeline stages for Example 21-5 on page 21-13.

21.7.3 Load multiple-short vector CDP RAW hazard example

In Example 21-6, the short vector FADDS is stalled in the Issue stage until the FLDM loads all

source registers required by the FADDS. In this case, the FADDS is stalled for three cycles.

Because the FADDS depends on the FLDM for only one register, S7, it does not have to wait

for completion of the FLDM. The S7 data is forwarded in cycle 6. The LEN field contains b011,

selecting a vector length of four iterations. The STRIDE field contains b00, selecting a vector

stride of one. The first source vector uses registers S7, S0, S1, and S2, and the only FADDS

source register loaded by the FLDM is S7. This example is based on the assumption that the

remaining source and destination registers are available to the FADDS in cycle 6.

Example 21-6 FLDM-short vector FADDS RAW hazard

FLDM [R2], {S7-S14}

FADDS S16, S7, S25

Table 21-8 lists the VFP11 pipeline stages of the FLDM and the first iteration of the short vector

FADDS for Example 21-6.

21.7.4 CDP-CDP RAW hazard example

In Example 21-7, the FADDS is stalled in the Issue stage for seven cycles until the FMULS data

is written and forwarded in cycle 10 to the Issue stage of the FADDS.

Example 21-7 FMULS-FADDS RAW hazard

FMULS S4, S1, S0

FADDS S5, S4, S3

Table 21-7 FLDM-FADDS RAW hazard

Instruction cycle number

Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

FLDM DIEM1M2WWWW-------

FADDS - D I I I I I I I E1 E2 E3 E4 E5 E6 E7

Table 21-8 FLDM-short vector FADDS RAW hazard

Instruction cycle number

Instruction 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

FLDM DIEM1M2WWWW---- ----

FADDS - D I I I I E1 E1 E1 E1 E2 E3 E4 E5 E6 E7 W

ARM ARM1176JZF-S User Manual

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