Clocking and Resets
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9.3 Clocking and resets with IEM
This section describes clocking and resets for the processor with IEM:
• Processor clocking with IEM
• Reset with IEM on page 9-8.
9.3.1 Processor clocking with IEM
Externally to the processor, you must connect CLKIN and FREECLKIN together.
It is possible to configure each of the four level two ports to instantiate an IEM register slice so
that the processor can have up to five clock domains, CLKIN, ACLKI, ACLKRW, ACLKP
and ACLKD. Because of the signals SYNCMODEREQI, SYNCMODEREQRW,
SYNCMODEREQP, SYNCMODEREQD, SYNCMODEACKI, SYNCMODEACKRW,
SYNCMODEACKP, and SYNCMODEACKD, it is possible to configure each IEM register
slice to operate synchronously or asynchronously.
The four level two interfaces and the VCore part of the IEM register slices use dedicated clock
enables, ACLKENI, ACLKENRW, ACLKENP, and ACLKEND.
If you configure an IEM register slice to operate asynchronously, its corresponding ACLKEN*
signal must be high. For example, when SYNCMODEACKI is low to indicate asynchronous
operation of the instruction port slice, the ACLKENI signal must be held high accordingly.
All clocks can be stopped indefinitely without loss of state.
Figure 9-3 on page 9-6 shows the clocks for the processor with IEM.
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