Memory Management Unit
ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-53
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6.13 MMU software-accessible registers
The MMU is controlled by the system control coprocessor, CP15 registers. Table 6-16, lists the
system control processor registers and references to their detailed descriptions. For more
information on the system control coprocessor, see Chapter 3 System Control Coprocessor.
Note
All the CP15 MMU registers, except CP15 c8, contain state that you read from using MRC
instructions and write to using MCR instructions. Registers c5 and c6 are also written by the
MMU. Reading CP15 c8 results in an Undefined exception.
Table 6-16 CP15 register functions
Register Cross reference
TLB Type Register c0, TLB Type Register on page 3-25
Control Register c1, Control Register on page 3-44
Non-Secure Access Control Register c1, Non-Secure Access Control Register on page 3-55
Translation Table Base Register 0 c2, Translation Table Base Register 0 on page 3-57
Translation Table Base Register 1 c2, Translation Table Base Register 1 on page 3-59
Translation Table Base Control Register c2, Translation Table Base Control Register on page 3-60
Domain Access Control Register c3, Domain Access Control Register on page 3-63
Data Fault Status Register (DFSR) c5, Data Fault Status Register on page 3-64
Instruction Fault Status Register (IFSR) c5, Instruction Fault Status Register on page 3-66
Fault Address Register (FAR) c6, Fault Address Register on page 3-68 and MMU fault checking on
page 6-29
Instruction Fault Address Register (IFAR) c6, Instruction Fault Address Register on page 3-69 and MMU fault checking
on page 6-29
TLB Operations Register c8, TLB Operations Register on page 3-86
TLB Lockdown Register c10, TLB Lockdown Register on page 3-100
Primary Region Remap Register c10, Memory region remap registers on page 3-101
Normal Memory Remap Register c10, Memory region remap registers on page 3-101
FCSE PID Register c13, FCSE PID Register on page 3-126
ContextID Register c13, Context ID Register on page 3-128.
Peripheral Port Remap Register c15, Peripheral Port Memory Remap Register on page 3-130
TLB Lockdown Index Register c15, TLB lockdown access registers on page 3-149
TLB Lockdown VA Register c15, TLB lockdown access registers on page 3-149
TLB Lockdown PA Register c15, TLB lockdown access registers on page 3-149
TLB Lockdown Attributes Register c15, TLB lockdown access registers on page 3-149
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